High-Speed FPGA Implementation of CORDIC Algorithm Using Carry Lookahead Adders

This paper introduces a hardware architecture for sine and cosine generation based on the CORDIC algorithm, optimized for FPGA implementation. It leverages a pipelined scale-free CORDIC datapath combined with carry look-ahead adders to reduce delay and improve speed over traditional ripple-carry adders. The design also incorporates hybrid CLA-RCA configurations and micro-rotation techniques to balance performance and hardware cost while enhancing computational efficiency.

Originally published by gnews